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AS4DDR264M72PBG |
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| Part Number | AS4DDR264M72PBG |
| Manufacturer | Austin Semiconductor |
| Description | On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits A7, A8, A9, A10, B7, Ax Input B8, B9, B10, C7, C8, C9, C10, D7 D8, D9, D10 DNU ... |
| Features |
DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package: • 255 Plastic Ball Grid Array (PBGA), 25 x 32mm • 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eightinternal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.1V power supply and I/O (VC... |
| Document |
 AS4DDR264M72PBG Data Sheet
PDF 310.42KB |
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Desde 2024. D4U Semiconductor.
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