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IDTCSPU877D |
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| Part Number | IDTCSPU877D |
| Manufacturer | Integrated Device Technology |
| Description | IDTCSPU877D • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 340MHz • Very low skew: ≤40ps... |
| Features |
DESCRIPTION:
IDTCSPU877D
• 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 340MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 52-Ball VFBGA and 40-pin MLF packages APPLICATIONS: • Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver • Along with SSTU32864/65/66, DDR2 register, p... |
| Document |
 IDTCSPU877D Data Sheet
PDF 179.41KB |
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| 6 | IDTCSPT855 |
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Desde 2024. D4U Semiconductor.
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