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74HC40104 Philips 4-bit bidirectional universal shift register Datasheet

CD74HC40104M 시프터 레지스터, 양방향 1 소자 4 비트 16-SOIC


Philips
74HC40104
Part Number 74HC40104
Manufacturer Philips
Description The 74HC/HCT40104 are high-speed Si-gate CMOS devices and are pin compatible with the “40104” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40104 are universal shift registers featuring parallel inputs, parallel outputs, shift-right and shift-left se...
Features
• Synchronous parallel or serial operating
• 3-state outputs
• Output capability: bus driver
• ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40104 are high-speed Si-gate CMOS devices and are pin compatible with the “40104” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40104 are universal shift registers featuring parallel inputs, parallel outputs, shift-right and shift-left serial inputs and 3-state outputs allowing the devices to be used in bus-organized systems. In the parallel-load mode (S0 and S1 are HIGH), data is loaded into the asso...

Document Datasheet 74HC40104 datasheet pdf (57.35KB)
Distributor Distributor
DigiKey
Stock 3537 In Stock
Price
1402 units: 291.27032 KRW
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74HC40104 Distributor

part
Rochester Electronics LLC
CD74HC40104M
시프터 레지스터, 양방향 1 소자 4 비트 16-SOIC
1402 units: 291.27032 KRW
Distributor
DigiKey

3537 In Stock
BuyNow BuyNow
part
Harris Semiconductor
CD74HC40104M
4-BIT UNIVERSAL BIDIRECTIONAL SHIFT REGISTER '
1000 units: 0.1837 USD
500 units: 0.1945 USD
100 units: 0.2031 USD
25 units: 0.2118 USD
1 units: 0.2161 USD
Distributor
Rochester Electronics

3537 In Stock
BuyNow BuyNow





74HC40104 Similar Datasheet

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The 74HC/HCT40102 are high-speed Si-gate CMOS devices and are pin compatible with the “40102” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40102 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40102” is configured as two cascaded 4-bit BCD counters and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on ...
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