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MCM63P631 |
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| Part Number | MCM63P631 |
| Manufacturer | Motorola |
| Description | Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, is used to latch a new external address. Used to initiate a READ, WRITE or chip deselect. Synchr... |
| Features |
can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P631 (burst sequence operates in linear or interleaved mode dependent upon state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self –timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off –chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable SW are pr... |
| Document |
 MCM63P631 Data Sheet
PDF 229.19KB |
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Desde 2024. D4U Semiconductor.
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