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ICS97U8770 |
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| Part Number | ICS97U8770 |
| Manufacturer | Renesas (https://www.renesas.com/) |
| Description | Terminal Name AGND AVDD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC Description Analog Ground Analog power Clock input with a (10K-100K Ohm) pulldown resistor Complentary clock input with a (10K-... |
| Features |
A and a 40-pin MLF.
ICS97U870 is a zero delay buffer that distributes a differential clock input pair(CLK_INT, CLK_INC) to ten differential pair of clock outputs(CLKT[0:9], CLKC[0:91) and one differential pair feedback clock outputs(FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks(CLK_INT, CLK_INC), the feedback clocks(FB_INT, FB_INC), the LVCMOS program pins(OE, OS) and the Analog Power input(AVDD). When OE is low, the outputs(except FB_OUTT/ FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS(Output Select) is a program pin th... |
| Document |
 ICS97U8770 Data Sheet
PDF 1.91MB |
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Desde 2024. D4U Semiconductor.
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