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74HC40105 nexperia 4-bit x 16-word FIFO register Datasheet

CD74HC40105M 비동기 FIFO 64(16 x 4) 단방향 16-SOIC


nexperia
74HC40105
74HC40105
Part Number 74HC40105
Manufacturer nexperia (https://www.nexperia.com/)
Description The 74HC40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by...
Features and benefits
• Independent asynchronous inputs and outputs
• Expandable in either direction
• Reset capability
• Status indicators on inputs and outputs
• 3-state outputs
• CMOS input levels
• Complies with JEDEC standard JESD7A
• ESD protection:

• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC40105D -40 °C to +125 °C Name SO16 Description plastic small outline package; 16 leads; body width 3.9 mm Version SOT...

Document Datasheet 74HC40105 datasheet pdf (310.10KB)
Distributor Distributor
DigiKey
Stock 680 In Stock
Price
520 units: 1047.7961 KRW
280 units: 1063.5215 KRW
80 units: 1072.6625 KRW
40 units: 1199.425 KRW
10 units: 1221.8 KRW
1 units: 1342 KRW
BuyNow BuyNow BuyNow (Manufacturer a Texas Instruments)




74HC40105 Distributor

part
Texas Instruments
CD74HC40105M
비동기 FIFO 64(16 x 4) 단방향 16-SOIC
520 units: 1047.7961 KRW
280 units: 1063.5215 KRW
80 units: 1072.6625 KRW
40 units: 1199.425 KRW
10 units: 1221.8 KRW
1 units: 1342 KRW
Distributor
DigiKey

680 In Stock
BuyNow BuyNow
part
Texas Instruments
CD74HC40105M96
Registers 4bits x 16words FIFO
1 units: 0.68 USD
10 units: 0.603 USD
100 units: 0.532 USD
500 units: 0.517 USD
1000 units: 0.493 USD
2500 units: 0.483 USD
5000 units: 0.441 USD
10000 units: 0.429 USD
Distributor
Mouser Electronics

2050 In Stock
BuyNow BuyNow
part
Harris Semiconductor
CD74HC40105EX
HIGH-SPEED CMOS LOGIC 4-BIT X 16-WORD FIFO REGISTER '
1000 units: 0.4061 USD
500 units: 0.43 USD
100 units: 0.4491 USD
25 units: 0.4682 USD
1 units: 0.4778 USD
Distributor
Rochester Electronics

1000 In Stock
BuyNow BuyNow
part
Philips Semiconductors
74HC40105D
FIFO, 16 x 4, Asynchronous, 16 Pin, Plastic, SOP
25 units: 0.63 USD
6 units: 0.84 USD
1 units: 1.05 USD
Distributor
Quest Components

40 In Stock
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part
Nexperia
74HC40105D,652
IC: digital; 4 bit x 16 word,storage register; CMOS; SMD; SO16
150 units: 1.19 USD
25 units: 1.3 USD
10 units: 1.5 USD
1 units: 1.78 USD
Distributor
TME

24 In Stock
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part
NXP Semiconductors
74HC40105D
4-BIT X 16-WORD FIFO REGISTER FIFO, 16X4, 600ns, Asynchronous, CMOS, PDSO16
No price available
Distributor
ComSIT Asia

10000 In Stock
No Longer Stocked
part
Philips Semiconductors
74HC40105D
INSTOCK
No price available
Distributor
Chip 1 Exchange

4490 In Stock
No Longer Stocked
part
Texas Instruments
CD74HC40105M
No price available
Distributor
Bristol Electronics

22 In Stock
No Longer Stocked
part
Harris Semiconductor
CD74HC40105M
IN STOCK SHIP TODAY
1000 units: 0.5 USD
100 units: 0.58 USD
1 units: 0.77 USD
Distributor
Component Electronics, Inc

105 In Stock
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74HC40105 Similar Datasheet

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The 74HC/HCT40102 are high-speed Si-gate CMOS devices and are pin compatible with the “40102” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40102 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40102” is configured as two cascaded 4-bit BCD counters and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on ...
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The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition re...
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The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition re...
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8-bit synchronous binary down counter
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition re...
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The 74HC/HCT40104 are high-speed Si-gate CMOS devices and are pin compatible with the “40104” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40104 are universal shift registers featuring parallel inputs, parallel outputs, shift-right and shift-left serial inputs and 3-state outputs allowing the devices to be used in bus-organized systems. In the parallel-load mode (S0 and S1 are HIGH), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge wit...
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4-bit x 16-word FIFO register
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the logic 0 state and sees a logic 1 in the preceding flip-flop, it g...
74HC40105D
manufacturer
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4-bit x 16-word FIFO register
The 74HC40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a c...
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