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M12L128168A-5TVAG2S |
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| Part Number | M12L128168A-5TVAG2S |
| Manufacturer | ESMT |
| Description | The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O... |
| Features |
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh (self refresh is not supported for VA grade) Refresh - 64 ms refresh period (4K cycle) for V grade -16 ms refresh period (4K cycle) for VA grade M12L128168A (2S) Automotive Grade 2M x 16 Bit x 4 Banks S... |
| Document |
 M12L128168A-5TVAG2S Data Sheet
PDF 1.02MB |
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | M12L128168A-5TVG2S |
ESMT |
2M x 16 Bit x 4 Banks Synchronous DRAM |
|
| 2 | M12L128168A-5TG |
ESMT |
2M x 16 Bit x 4 Banks Synchronous DRAM |
|
| 3 | M12L128168A-5TG2N |
ESMT |
2M x 16 Bit x 4 Banks Synchronous DRAM |
|
| 4 | M12L128168A-5TG2S |
ESMT |
2M x 16 Bit x 4 Banks Synchronous DRAM |
|
| 5 | M12L128168A-5BG |
ESMT |
2M x 16 Bit x 4 Banks Synchronous DRAM |
|
| 6 | M12L128168A-5BG2N |
ESMT |
2M x 16 Bit x 4 Banks Synchronous DRAM |
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Desde 2024. D4U Semiconductor.
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