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CY7C1520KV18 |
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| Part Number | CY7C1520KV18 |
| Manufacturer | Cypress Semiconductor |
| Description | CY7C1518KV18 CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture Features ■ 72-Mbit density (4M × 18, 2M × 36) ■ 333 MHz clock for high bandwi... |
| Features |
■ 72-Mbit density (4M × 18, 2M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Synchronous internally self-timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR-I device w... |
| Document |
 CY7C1520KV18 Data Sheet
PDF 604.50KB |
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Desde 2024. D4U Semiconductor.
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