Busque con el número de pieza junto con el fabricante o la descripción
74LS112A |
Click to view a larger image
| Part Number | 74LS112A |
| Manufacturer | Motorola |
| Description | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the ... |
| Features |
individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
SN54/74LS112A
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q 5(9)
CLEAR (CD) 15(14) J 3(11)
1(13) C... |
| Document |
 74LS112A Data Sheet
PDF 147.34KB |
Similar Datasheet
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | 74LS112 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops |
|
| 2 | 74LS112A |
Fairchild Semiconductor |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
|
| 3 | 74LS11 |
Fairchild Semiconductor |
Triple 3-Input AND Gate |
|
| 4 | 74LS114A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 5 | 74LS10 |
ON Semiconductor |
TRIPLE 3-INPUT NAND GATE |
|
| 6 | 74LS10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate |
|
Desde 2024. D4U Semiconductor.
|