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CY7C1303BV18 |
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| Part Number | CY7C1303BV18 |
| Manufacturer | Cypress Semiconductor |
| Description | • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 2-Word Burst on all accesses • Double Data... |
| Features |
Functional Description
• Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port... |
| Document |
 CY7C1303BV18 Data Sheet
PDF 677.60KB |
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Desde 2024. D4U Semiconductor.
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