Features |
include independent (synchronous) output enable, glitchless switching, LOS monitor of input clocks, output clock division, and built-in format translation. These buffers can be paired with the Si534x clocks and jitter attenuators, the Si5332 clocks, and the Si5xx oscillators to deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank o |
Distributor | Stock | Price | Buy |
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No. | Part # | Manufacture | Description | Datasheet |
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Silicon Laboratories |
LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR |
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Skyworks |
Ultra-Low Additive Jitter Fanout Clock Buffers |
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Silicon Laboratories |
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR |
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Skyworks |
Ultra-Low Additive Jitter Fanout Clock Buffers |
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Silicon Laboratories |
DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR |
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Skyworks |
Ultra-Low Additive Jitter Fanout Clock Buffers |
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Silicon Laboratories |
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR |
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Skyworks |
Ultra-Low Additive Jitter Fanout Clock Buffers |
|
|
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Silicon Laboratories |
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR |
|
|
|
Skyworks |
Ultra-Low Additive Jitter Fanout Clock Buffers |
|
|
|
Silicon Laboratories |
1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR |
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|
|
Skyworks |
Ultra-Low Additive Jitter Fanout Clock Buffers |
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