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SNJ54HC10J Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATES Datasheet

SNJ54HC10J IC GATE NAND 3CH 3-INP 14CDIP


Texas Instruments
SNJ54HC10J
Part Number SNJ54HC10J
Manufacturer Texas Instruments (https://www.ti.com/)
Description ordering information NC − No internal connection The ’HC10 devices contain three independent 3-input NAND gates. They perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 S...
Features SOIC − D Reel of 2500 Reel of 250 SN74HC10DR SN74HC10DT HC10 −40°C to 85°C SOP − NS SSOP − DB Reel of 2000 Reel of 2000 SN74HC10NSR SN74HC10DBR HC10 HC10 Tube of 90 SN74HC10PW TSSOP − PW Reel of 2000 Reel of 250 SN74HC10PWR SN74HC10PWT HC10 CDIP − J Tube of 25 SNJ54HC10J SNJ54HC10J −55°C to 125°C CFP − W Tube of 150 SNJ54HC10W SNJ54HC10W LCCC − FK Tube of 55 SNJ54HC10FK SNJ54HC10FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice...

Document Datasheet SNJ54HC10J datasheet pdf (1.24MB)
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28 units: 10.92 USD
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SNJ54HC10J Distributor

Texas Instruments
SNJ54HC10J
IC GATE NAND 3CH 3-INP 14CDIP
28 units: 10.92 USD
Distributor
DigiKey

333 In Stock
BuyNow BuyNow
part
Texas Instruments
SNJ54HC10J
54HC10 Triple 3-Input Positive-NAND Gates
1000 units: 9.37 USD
500 units: 9.92 USD
100 units: 10.36 USD
25 units: 10.8 USD
1 units: 11.02 USD
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Rochester Electronics

333 In Stock
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Texas Instruments
SNJ54HC10J
Logic Circuit, 3 3-Input NAND, HC-CMOS, 14 Pin, Ceramic, DIP
56 units: 8.433 USD
25 units: 9.1358 USD
1 units: 14.055 USD
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Quest Components

80 In Stock
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Texas Instruments
SNJ54HC10J
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Bristol Electronics

1 In Stock
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SNJ54HC10J Similar Datasheet

Part Number Description
SNJ54HC109FK
manufacturer
Texas Instruments
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops...
SNJ54HC109J
manufacturer
Texas Instruments
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops...
SNJ54HC109W
manufacturer
Texas Instruments
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops...
SNJ54HC10FK
manufacturer
Texas Instruments
TRIPLE 3-INPUT POSITIVE-NAND GATES
ordering information NC − No internal connection The ’HC10 devices contain three independent 3-input NAND gates. They perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC10N SN74HC10N Tube of 50 SN74HC10D SOIC − D Reel of 2500 Reel of 250 SN74HC10DR SN74HC10DT HC10 −40°C to 85°C SOP − NS SSOP − DB Reel of 2000 Reel of 2000 SN74HC10NSR SN74HC10DBR HC10 HC10 Tube of 90 SN74HC10PW TSSOP − PW Reel of 2000 Reel of 250 SN74HC10PWR SN74HC10PWT HC10 CDIP − J Tube of 25 SNJ54HC10J SNJ54HC10J −55°C to 125°C CFP − W Tube of 150 SNJ54HC10W SNJ54...
SNJ54HC10W
manufacturer
Texas Instruments
TRIPLE 3-INPUT POSITIVE-NAND GATES
ordering information NC − No internal connection The ’HC10 devices contain three independent 3-input NAND gates. They perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC10N SN74HC10N Tube of 50 SN74HC10D SOIC − D Reel of 2500 Reel of 250 SN74HC10DR SN74HC10DT HC10 −40°C to 85°C SOP − NS SSOP − DB Reel of 2000 Reel of 2000 SN74HC10NSR SN74HC10DBR HC10 HC10 Tube of 90 SN74HC10PW TSSOP − PW Reel of 2000 Reel of 250 SN74HC10PWR SN74HC10PWT HC10 CDIP − J Tube of 25 SNJ54HC10J SNJ54HC10J −55°C to 125°C CFP − W Tube of 150 SNJ54HC10W SNJ54...
SNJ54HC112FK
manufacturer
Texas Instruments
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
ordering information The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops ...
SNJ54HC112J
manufacturer
Texas Instruments
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
ordering information The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops ...
SNJ54HC112W
manufacturer
Texas Instruments
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
ordering information The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops ...
SNJ54HC148FK
manufacturer
Texas Instruments
8-LINE TO 3-LINE PRIORITY ENCODERS
ordering information The ’HC148 devices feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. These devices encode eight data lines to 3-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. Data inputs and outputs are active at the low logic level. SN54HC148, SN74HC148 8ĆLINE TO 3ĆLINE PRIORITY ENCODERS SCLS109G − MARCH 1984 − REVISED APRIL 2004 SN54HC148 . . . J OR W PACKAGE SN74HC148 . . . D, DW, N, OR NS PACKAGE (TOP VIEW) 41 52 63 74 EI 5 A2 6 A1 7 GND 8 16 VCC 15 EO 14 GS 13 3 12 2 11 1 10 0 9 A0 SN54HC148 . . . FK PACK...




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