logo

TC74AC109P Toshiba Dual J-K Flip-Flop Datasheet

TC74AC109P


Toshiba
TC74AC109P
Part Number TC74AC109P
Manufacturer Toshiba (https://www.toshiba.com/)
Description TC74AC109P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC109P, TC74AC109F Dual J-K Flip Flop with Preset and Clear The TC74AC109 is an advanced high speed CMOS DUAL J- K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high ...
Features
• High speed: fmax = 200 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Pin and function compatible with 74F109 Pin Assignment TC74AC109P TC74AC109F Weight DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Start of commercial production 1987-05 1 2014-03-01 IEC Logic Symbol TC74AC109P...

Document Datasheet TC74AC109P datasheet pdf (284.74KB)
Distributor Distributor
Quest Components
Stock 261 In Stock
Price
85 units: 0.595 USD
22 units: 0.714 USD
1 units: 1.19 USD
BuyNow BuyNow BuyNow (Manufacturer a Toshiba America Electronic Components)




TC74AC109P Distributor

Toshiba America Electronic Components
TC74AC109P
85 units: 0.595 USD
22 units: 0.714 USD
1 units: 1.19 USD
Distributor
Quest Components

261 In Stock
BuyNow BuyNow





Similar Datasheet

Part Number Description
TC74AC109F
manufacturer
Toshiba
Dual J-K Flip-Flop
TC74AC109P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC109P, TC74AC109F Dual J-K Flip Flop with Preset and Clear The TC74AC109 is an advanced high speed CMOS DUAL J- K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. In accordance with the logic level given J and K input this device changes state on positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits ...
TC74AC10F
manufacturer
Toshiba Semiconductor
Triple 3-Input NAND Gate
TC74AC10P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC10P, TC74AC10F Triple 3-Input NAND Gate The TC74AC10 is an advanced high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 5.0 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = ...
TC74AC10FN
manufacturer
Toshiba Semiconductor
Triple 3-Input NAND Gate
TC74AC10P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC10P,TC74AC10F,TC74AC10FN Triple 3-Input NAND Gate The TC74AC10 is an advanced high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 5.0 ns (typ.) at VCC = 5 V • Low power dissip...
TC74AC10P
manufacturer
Toshiba Semiconductor
Triple 3-Input NAND Gate
TC74AC10P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC10P, TC74AC10F Triple 3-Input NAND Gate The TC74AC10 is an advanced high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 5.0 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = ...




logo    Since 2024. D4U Semiconductor.   |   Contact Us   |   Privacy Policy