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HD74HC564P Hitachi Semiconductor Octal D-type Flip-Flop Datasheet


Hitachi Semiconductor
HD74HC564P
Part Number HD74HC564P
Manufacturer Hitachi Semiconductor
Description These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only that the former has inverting outputs and the latter has noninvertering outputs. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on ...
Features
• High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Outputs Output Control Clock Data HD74HC564 HD74HD574 L H L H L L H L L L H X X Q0 Q0 X Z Z Q0 : level of Q before the indicated Steady-sate input conditions were established. Q0 : complement of Q0 or level of Q before the indicated Steady-state input Conditions were established. HD74HC564/HD74HC574 ...

Document Datasheet HD74HC564P datasheet pdf (65.49KB)


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HD74HC563
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When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • • • • • High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Q...
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When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Lo...
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Octal D-type Flip-Flops
These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only that the former has inverting outputs and the latter has noninvertering outputs. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide ...
HD74HC564P
manufacturer
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Octal D-type Flip-Flops
These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only that the former has inverting outputs and the latter has noninvertering outputs. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features • High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads • Wide ...




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