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74HC40103 NXP 8-bit synchronous binary down counter Datasheet

74HC40103PW,118 카운터 IC 이진 카운터 1 소자 8 비트 포지티브 에지 16-TSSOP


NXP
74HC40103
74HC40103
Part Number 74HC40103
Manufacturer NXP (https://www.nxp.com/)
Description The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on eac...
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Document Datasheet 74HC40103 datasheet pdf (189.56KB)
Distributor Distributor
DigiKey
Stock 1035 In Stock
Price
1000 units: 708.633 KRW
500 units: 897.598 KRW
250 units: 1015.68 KRW
100 units: 1086.62 KRW
25 units: 1323.04 KRW
10 units: 1393.4 KRW
1 units: 1558 KRW
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74HC40103 Distributor

part
Nexperia
74HC40103PW,118
SYNC BINARY DOWN COUNTER, -40TO125DEG C
2500 units: 524 KRW
1000 units: 636 KRW
500 units: 809 KRW
100 units: 916 KRW
10 units: 1178 KRW
1 units: 1390 KRW
Distributor
element14 Asia-Pacific

2018 In Stock
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part
Nexperia
74HC40103PW,118
카운터 IC 이진 카운터 1 소자 8 비트 포지티브 에지 16-TSSOP
1000 units: 708.633 KRW
500 units: 897.598 KRW
250 units: 1015.68 KRW
100 units: 1086.62 KRW
25 units: 1323.04 KRW
10 units: 1393.4 KRW
1 units: 1558 KRW
Distributor
DigiKey

1035 In Stock
BuyNow BuyNow
part
Nexperia
74HC40103PW,118
Counter Single 8-Bit Sync/Async Binary Down 16-Pin TSSOP T/R (Alt: 74HC40103PW,118)
125000 units: 0.49882 USD
62500 units: 0.51084 USD
25000 units: 0.52346 USD
12500 units: 0.53671 USD
7500 units: 0.54359 USD
5000 units: 0.55065 USD
2500 units: 0.55789 USD
Distributor
Avnet Asia

0 In Stock
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part
Nexperia
74HC40103D,653
Counter ICs 74HC40103D/SOT109/SO16
1 units: 1.13 USD
10 units: 0.963 USD
100 units: 0.742 USD
500 units: 0.644 USD
1000 units: 0.516 USD
2500 units: 0.476 USD
5000 units: 0.461 USD
10000 units: 0.43 USD
Distributor
Mouser Electronics

20209 In Stock
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part
Nexperia
74HC40103PW,118
Counter Single 8-Bit Sync/Async Binary Down 16-Pin TSSOP T/R
25000 units: 0.2807 USD
10000 units: 0.2837 USD
5000 units: 0.3085 USD
2500 units: 0.3115 USD
1000 units: 0.355 USD
500 units: 0.4038 USD
256 units: 0.4279 USD
Distributor
Arrow Electronics

6500 In Stock
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part
Texas Instruments
CD74HC40103M96
Counter Single 8-Bit Sync/Async Binary Down 16-Pin SOIC T/R
1 units: 0.586 USD
10 units: 0.525 USD
50 units: 0.5 USD
Distributor
Chip1Stop

2243 In Stock
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part
Nexperia
74HC40103PW,118
Counter Single 8-Bit Sync/Async Binary Down 16-Pin TSSOP T/R
184 units: 0.542 USD
Distributor
Verical

2229 In Stock
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part
Texas Instruments
CD74HC40103QM96EP
CD74HC40103-EP Enhanced Product High Speed Cmos Logic 8-Stage Synchronous Down Counters
1000 units: 2.13 USD
500 units: 2.25 USD
100 units: 2.35 USD
25 units: 2.45 USD
1 units: 2.5 USD
Distributor
Rochester Electronics

91 In Stock
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part
Nexperia
74HC40103D,653
Counter ICs SOT109-1 DOWN COUNTER 8-BIT
2500 units: 0.354 USD
5000 units: 0.347 USD
7500 units: 0.341 USD
12500 units: 0.334 USD
25000 units: 0.327 USD
Distributor
TTI

0 In Stock
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part
Philips Semiconductors
74HC40103D
Counter, Down, 8 Bit Binary, 16 Pin, Plastic, SOP
94 units: 0.42 USD
21 units: 0.54 USD
1 units: 0.9 USD
Distributor
Quest Components

251 In Stock
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74HC40103 Similar Datasheet

Part Number Description
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The 74HC/HCT40102 are high-speed Si-gate CMOS devices and are pin compatible with the “40102” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40102 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40102” is configured as two cascaded 4-bit BCD counters and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on ...
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8-bit synchronous binary down counter
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition re...
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The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition re...
74HC40103PW
manufacturer
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8-bit synchronous binary down counter
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition re...
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The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the logic 0 state and sees a logic 1 in the preceding flip-flop, it g...
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4-bit x 16-word FIFO register
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74HC40105D
manufacturer
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4-bit x 16-word FIFO register
The 74HC40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a c...
74HC4015
manufacturer
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The 74HC/HCT4015 are high-speed Si-gate CMOS devices and are pin compatible with the “4015” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4015 are dual edge-triggered 4-bit static shift registers (serial-to-parallel converters). Each shift register has a serial data input (1D and 2D), a clock input (1CP and 2CP), four fully buffered parallel outputs (1Q0 to 1Q3 and 2Q0 to 2Q3) and an overriding asynchronous master reset (1MR and 2MR). Information present on nD is shifted to the first register position, and all data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and...




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