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IS43TR81280BL ISSI 1Gb DDR3 SDRAM Datasheet

IS43TR81280BL-107MBL IC DRAM 1GBIT PAR 78TWBGA


ISSI
IS43TR81280BL
Part Number IS43TR81280BL
Manufacturer ISSI
Description - JEDEC Standard Symbol Type Function CK, CK# CKE CS# ODT RAS#. CAS#. WE# DM, (DMU), (DML) BA0 - BA2 A0 - A13 A10 / AP A12 / BC# RESET# DQ(DQL, DQU) Input Input Input Input Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing ...
Features
 Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
 Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V - Backward compatible to 1.5V
 High speed data transfer rates with system frequency up to 1066 MHz
 8 internal banks for concurrent operation
 8n-bit pre-fetch architecture
 Programmable CAS Latency
 Programmable Additive Latency: 0, CL-1,CL-2
 Programmable CAS WRITE latency (CWL) based on tCK
 Programmable Burst Length: 4 and 8
 Programmable Burst Sequence: Sequential or Interleave
 BL switch on the fly
 Auto Self Refresh(ASR)
 Self Refresh Temperature(SRT) OPTIONS
 Configurati...

Document Datasheet IS43TR81280BL datasheet pdf (3.11MB)
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DigiKey
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IS43TR81280BL Distributor

part
Integrated Silicon Solution Inc
IS43TR81280BL-107MBL
IC DRAM 1GBIT PAR 78TWBGA
No price available
Distributor
DigiKey

0 In Stock
BuyNow BuyNow
part
Integrated Silicon Solution Inc
IS43TR81280BL-125KBL
DRAM 1G, 1.35V, DDR3L, 128Mx8, 1600MT/s @ 11-11-11, 78 ball BGA (8mm x10.5mm) RoHS
1 units: 3.89 USD
10 units: 3.53 USD
100 units: 3.08 USD
242 units: 3.06 USD
484 units: 2.95 USD
968 units: 2.8 USD
2662 units: 2.67 USD
Distributor
Mouser Electronics

0 In Stock
No Longer Stocked
part
Integrated Silicon Solution Inc
IS43TR81280BL-125KBL-TR
(Alt: IS43TR81280BL-125KBL-TR)
No price available
Distributor
Avnet Silica

0 In Stock
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IS43TR81280BL Similar Datasheet

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- JEDEC Standard Symbol Type Function CK, CK# CKE CS# ODT RAS#. CAS#. WE# DM, (DMU), (DML) BA0 - BA2 A0 - A13 A10 / AP A12 / BC# RESET# DQ(DQL, DQU) Input Input Input Input Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and SelfRefresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stabl...
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- JEDEC Standard Symbol Type Function CK, CK# CKE Input Input CS# ODT Input Input RAS#. CAS#. WE# DM, (DMU), (DML) BA0 - BA2 A0 - A13 Input Input Input Input A10 / AP Input A12 / BC# RESET# Input Input DQ(DQL, DQU) DQS, DQS#, DQSU, DQSU#, DQSL, DQSL# Input / Output Input / Output TDQS, TDQS# Output NC Clock: CK and CK# are differential clock inputs. Al...




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